Conventional memory systems may comprise a low voltage select line and a high voltage deselect line for accessing a desired word or bit line (generally referred to as memory access lines). A selected memory access line in an array is coupled to the select line, and non-selected memory access lines are coupled to the deselect line. Conventional two transistor decoder circuits used to select memory access lines may comprise a p-channel field effect (PFET) transistor and an n-channel field effect (NFET) transistor. NFET transistors may be advantageous for delivering low voltages, and PFET transistors may be advantageous for delivering high voltages. In the example conventional system described, the circuit works most efficiently when the NFET transistor connects the access line to the select line when activated, and the PFET transistor connects the access line to the deselect line when activated.
However, with some memory technologies, for example, bi-polar resistive RAM, it may be advantageous to allow current to pass through a memory cell in opposite directions during different phases of operation. In these situations, the conventional two-transistor decoder may not deliver current efficiently for all directions of current flow. An additional PFET transistor may be placed in parallel with the NFET transistor, and an additional NFET transistor may be placed in parallel with the PFET transistor to form CMOS transmission gates to improve current efficiency, but this solution would incur two additional transistors and two additional wires per access line. The increase in cost and space required for the conventional decoder architecture may be undesirable in applications where circuit compactness and simplicity are needed.